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INTEGRATED CIRCUITS
DATA SHEET
SAA5233 Dual standard PDC decoder
Objective specification File under Integrated Circuits, IC02 June 1994
Philips Semiconductors
Philips Semiconductors
Objective specification
Dual standard PDC decoder
FEATURES * Digital data slicer * Acquisition and decoding of VPS data (EBU PDC System A) * Acquisition and decoding of Teletext packet 8/30/2 data (EBU PDC System B) * Separate storage of VPS data and packet 8/30/2 allowing dual standard PDC decoders * I2C-bus interface with automatic word address increment * Programmable interrupt for data received * Programmable error level detection * Single +5 V power supply. GENERAL DESCRIPTION The SAA5233 is a dual standard Program Delivery Control (PDC) decoder, allowing the reception and decoding of both VPS data (EBU PDC System A) and Teletext packet 8/30/2 data (EBU PDC System B). It is intended for use in European video recorders which are manually programmed, so that they receive broadcast real time switching signals for accurate timing of program recording. QUICK REFERENCE DATA SYMBOL VDD IDD fclk Vsync Vvid(p-p) Tamb Tstg supply voltage supply current crystal input frequency CVBS sync voltage amplitude CVBS video voltage amplitude (peak-to-peak value) operating ambient temperature storage temperature PARAMETER 4.5 - - 0.1 0.7 -20 -55 MIN. 5.0 30 27 0.3 1.0 - - TYP. 5.5 45 - 0.6 1.4 +70 +125 MAX.
SAA5233
UNIT V mA MHz V V C C
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA5233P SAA5233T 16 20 PIN POSITION DIP16 SO20L MATERIAL plastic plastic CODE SOT38-1 SOT163-1
June 1994
2
Philips Semiconductors
Objective specification
Dual standard PDC decoder
BLOCK DIAGRAM
SAA5233
SCL
handbook, full pagewidth
SDA 13
12
AD
14
I2 C BUS INTERFACE
MEMORY INTERFACE AND RAM
INT
15
INTERRUPT CONTROL
SAA5233
VDD V SS1 V SS2 V SS3 V SS4 V SS5
4 TELETEXT AND VPS CONTROL
5
8/30/2 ACQUISITION AND DECODING
9 10 11 16 DATA SLICER AND CLOCK REGENERATOR POWER ON RESET 13.5 MHz 27 MHz 1.125 MHz 27 MHz OSCILLATOR AND DIVIDER 6 7 8 ANALOGUE TO DIGITAL CONVERTER INPUT CLAMP AND SYNC SEPARATOR 1 2 3
MLB725
VPS ACQUISITION AND DECODING
PLL AND TIMING
OSCOUT OSCIN OSCGND
CVBS BLACK IREF
Fig.1 Block diagram; pin numbers for DIP16.
June 1994
3
Philips Semiconductors
Objective specification
Dual standard PDC decoder
PINNING PIN SYMBOL DIP16 CVBS BLACK n.c. IREF VDD VSS1 OSCOUT n.c. OSCIN OSCGND VSS2 VSS3 n.c. VSS4 SCL SDA i.c. AD INT VSS5 1 2 - 3 4 5 6 - 7 8 9 10 - 11 12 13 - 14 15 16 SO20L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 composite video input video black level storage pin not connected reference current input +5 V supply 0 V ground 1 (main ground pin) 27 MHz crystal oscillator output not connected 27 MHz crystal oscillator input 27 MHz crystal oscillator ground 0 V ground 2; connect to VSS1 0 V ground 3; connect to VSS1 not connected connect to VSS1 in normal operation serial clock open-drain input for I2C-bus serial data open-drain input/output for I2C-bus DESCRIPTION
SAA5233
internally connected; do not connect in normal operation programmable I2C-bus address bit input interrupt open-drain output connect to VSS1 in normal operation
handbook, halfpage
handbook, halfpage
CVBS BLACK IREF VDD V SS1 OSCOUT OSCIN OSCGND
1 2 3 4
16 V SS5 15 INT 14 AD 13 SDA
CVBS BLACK n.c. IREF VDD V SS1 OSCOUT n.c. OSCIN
1 2 3 4 5
20 V SS5 19 INT 18 AD 17 i.c.
SAA5233
5 6 7 8
MLB726
12 SCL 11 V SS4 10 V SS3 9 V SS2
16 SDA
SAA5233
6 7 8 9 15 SCL 14 V SS4 13 n.c. 12 V SS3 11 V SS2
MLB727
OSCGND 10
Fig.2 Pin configuration; DIP16.
Fig.3 Pin configuration; SO20L.
June 1994
4
Philips Semiconductors
Objective specification
Dual standard PDC decoder
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VImax VOmax IIOmax IOmax Tamb Tstg supply voltage maximum input voltage (any input) maximum output voltage (any output) maximum DC input or output diode current maximum output current (any output) operating ambient temperature storage temperature PARAMETER MIN. -0.3 -0.3 -0.3 - - -20 -55
SAA5233
MAX. +6.5 VDD + 0.3 VDD + 0.3 20 10 +70 +125 V V V
UNIT
mA mA C C
June 1994
5
Philips Semiconductors
Objective specification
Dual standard PDC decoder
QUALITY AND RELIABILITY
SAA5233
This device will meet the requirements of the "Philips Semiconductors General Quality Specification SNW-FQ-611E" in accordance with "Quality Reference Pocketbook (order number 9398 510 34011)". The principal requirements are as shown in Tables 1 to 4. Group A Table 1 Acceptance tests per lot. TEST Mechanical Electrical cumulative target: <100 ppm cumulative target: <100 ppm REQUIREMENTS(1)
Group B Table 2 Processability tests (by package family). TEST Solderability Mechanical Solder heat resistance <7% LTPD <15% LTPD <15% LTPD REQUIREMENTS(1)
Group C Table 3 Reliability tests (by process family). TEST Operational life Humidity life CONDITIONS 168 hours at Tj = 150 C temperature, humidity, bias (1000 hours, 85 C, 85% RH or equivalent test) Tstg(min) to Tstg(max) REQUIREMENTS(1) <1500 FPM; equivalent to <100 FITS at Tj = 70 C <2000 FPM
Temperature cycling performance
<2000 FPM
Table 4 Reliability tests (by device type). TEST ESD and latch-up CONDITIONS ESD Human body model 2000 V; 100 pF; 1.5 k ESD Machine model 200 V; 200 pF; 0 latch-up 100 mA; 1.5 x VDD (absolute maximum) Note to Tables 1 to 4. 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard. REQUIREMENTS(1) <15% LTPD <15% LTPD <15% LTPD
June 1994
6
Philips Semiconductors
Objective specification
Dual standard PDC decoder
CHARACTERISTICS VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDD Inputs CVBS Vsync Vvid(p-p) Vdat(text) Vdat(vps) Zsource ZI CI IREF Rgnd VIREF AD VIL VIH ILI CI SCL VIL VIH ILI CI fclk tr tf LOW level input voltage HIGH level input voltage input leakage current input capacitance clock frequency input rise time input fall time 0.3VDD to 0.7VDD 0.7VDD to 0.3VDD VI = 0 to VDD -0.3 0.7VDD -10 - 0 - - - - - - - - - LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = 0 to VDD -0.3 0.7VDD -10 - - - - - resistor to ground input reference voltage - - 27 0.5VDD - - sync voltage amplitude video voltage amplitude (peak-to-peak value) Teletext data voltage amplitude VPS data voltage amplitude source impedance input impedance input capacitance 0.1 0.7 0.30 0.30 - 2.5 - 0.3 1.0 0.46 0.50 - 5.0 - 0.6 1.4 0.70 0.70 250 - 10 supply voltage supply current 4.5 - 5.0 30 5.5 45 PARAMETER CONDITIONS MIN. TYP.
SAA5233
MAX.
UNIT
V mA
V V V V k pF
k V
+0.3VDD VDD + 0.3 +10 10
V V A pF
+0.3VDD VDD + 0.3 +10 10 100 1000 300
V V A pF kHz ns ns
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
SYMBOL Outputs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
INT (OPEN-DRAIN OUTPUT) VPU VOL IOL CL tf pull-up voltage at pin LOW level output voltage LOW level output current load capacitance output fall time CL = 100 pF; 0.7VDD to 0.3VDD IOL = 3 mA - 0 - - - - - - - - VDD 0.4 4.0 400 100 V mA pF ns
Inputs/Outputs BLACK Cblack ILI VIL VIH ILI CI CL tr tf VOL tf storage capacitor to ground input leakage current VI = 0 to VDD - -10 -0.3 0.7VDD VI = 0 to VDD -10 - - 0.3VDD to 0.7VDD 0.7VDD to 0.3VDD IOL = 3 mA CL = 400 pF; 0.7VDD to 0.3VDD - - 0 - 100 - - - - - - - - - - - +10 nF A V V A pF pF ns ns V ns
SDA (OPEN-DRAIN OUTPUT) LOW level input voltage HIGH level input voltage input leakage current input capacitance load capacitance input rise time input fall time LOW level output voltage output fall time (OSCIN; OSCOUT) - - - - 1.0 1.0 - 1 - - 10 - pF pF V +0.3VDD VDD + 0.3 +10 10 400 1000 300 0.4 200
CRYSTAL OSCILLATOR
Vosc Gv CI Cfb
oscillator voltage amplitude (peak-to-peak value) small signal voltage gain input capacitance feedback capacitance
June 1994
8
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus timing (see Fig.4) fclk tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Note 1. After this time the first clock pulse is generated. SCL clock frequency bus free time between a STOP and START repeated START hold time SCL clock LOW time SCL clock HIGH time set-up time for a repeated START data hold time data set-up time SDA, SCL input rise time SDA, SCL input fall time set-up time for STOP 0.3VDD to 0.7VDD 0.7VDD to 0.3VDD note 1 0 4.7 4.0 4.7 4.0 4.7 0 250 - - 4.0 - - - - - - - - - - - 100 - - - - - - - 1 000 300 - kHz s s s s s ns ns ns ns s
andbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL t HIGH t SU;DAT
t HD;STA
tr
t HD;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.4 I2C-bus timing diagram.
June 1994
9
Philips Semiconductors
Objective specification
Dual standard PDC decoder
FUNCTIONAL DESCRIPTION Control of device The function of the device is controlled via the I2C-bus. Pin AD provides a choice of two alternative addresses. The PDC acquisition section requires little software control apart from enabling the interrupts which occur when data is found. Interrupts can be enabled for either Teletext packet 8/30/2 or VPS and both can be enabled to allow for the presence of both standards being transmitted on the same TV channel. The interrupt register is accessed as address 01 WRITE, see Section "Register 01: Interrupt (reset state X00X XXXX)". When an interrupt is signalled, a bit is set in the status register to indicate its source. Information about the received PDC data is given in the status register D5 and D6. The microcontroller must service the `data received' interrupts within 40 ms (VPS) or 200 ms (Teletext packet 8/30/2), since new data may be written after this period. The status register is accessed as address 00 READ; see Section "Register 00:Control/Status (reset state XXX0 XX00)". When the status register has been read the data received flags and interrupt signal are reset. Data of both types is constantly received and stored, but can be selectively acquired by setting bits D1 and D0 of the control register. This allows acquisition of only Teletext packet 8/30/2 on every VBI line or only VPS data on every VBI line. The control register is accessed as address 00 WRITE, see Section "Register 00:Control/Status (reset state XXX0 XX00)". Storage of PDC data The PDC data memory is accessed at address 02 (HEX) to 31 (HEX). The exact addresses of Teletext packet 8/30/2 and VPS data is shown in Table 5. TELETEXT DATA The Teletext packet 8/30/2 data is stored after hardware Hamming correction. There are 4 data bits stored in the lower nibble of each byte in address 11 (HEX) to 1D (HEX); see Table 13, in the order shown in Table 5. The status message, which is odd parity coded, is stored as a byte which represents a Teletext character in address 1E (HEX) to 31 (HEX); see Table 14. VPS DATA The VPS data from Line 16 is stored in register address 02 (HEX) to 0F (HEX) in the order shown in Table 5. VPS
SAA5233
data is biphase decoded and stored with 4 data bits stored in the lower nibble of each byte, in the same way as Teletext packet 8/30/2 data; see Tables 11 and 12. In addition to the VCR data, Word 4 (Program Source Identification, ASCII sequential) is stored, which may be useful for future applications. The stored data is read via the I2C-bus in the normal way. Multiple reception/majority error correction of the data is the responsibility of the control software, the device simply stores the data as transmitted after Hamming or biphase decoding. As both VPS and Teletext packet 8/30/2 signals are stored separately, it is possible to deal with future situations where both EBU PDC System A and EBU PDC System B transmissions may be present on the same TV channel, the defaults and level of service being chosen by the software control. Error indication Indication of errors in the received data is given in two ways and is programmable by setting bit D4 in the control register. The first is a flag to indicate Hamming or biphase errors and is stored with the related data in bit 0 of the upper nibble of the data byte. The second is no interrupt which is sent to the microcontroller but the data signal quality bit (D7) is set. The level of interrupt is controlled by the Interrupt Error Level bit which is D4 of the control register. If this bit is not set then an interrupt only occurs if an error free line of either Teletext packet 8/30/2 or VPS data is received and stored in RAM. If this bit is set then an interrupt occurs if the correct framing code and Teletext packet header 8/30/2 is found, or the correct start code for VPS data is found. The data is then stored in the RAM with any errors indicated in the upper nibble. This may be used by more sophisticated software, which could decide the importance of an error in a particular nibble. I2C-bus interface FEATURES * Standard I2C-bus slave transceiver * Operates from 0 to 100 kHz * Acknowledge function is performed * Auto-increment between registers and direct addressing * Selectable I2C-bus slave address dependent on address pin AD.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
Register map
SAA5233
The data received when address locations 00 (HEX) to 31 (HEX) are read or written is shown in Table 5. Table 5 Register map. ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E : 31 Note 1. For the address range 02H to 0FH, even addresses hold the least significant nibble and odd addresses hold the most significant nibble. BXX refers to byte definitions, EBU specification of the domestic video PDC system. DATA(1) control/status interrupt VPS B5 VPS B5 VPS B11 VPS B11 VPS B12 VPS B12 VPS B13 VPS B13 VPS B14 VPS B14 VPS B15 VPS B15 VPS B4 VPS B4 - 8/30/2 B13 8/30/2 B14 8/30/2 B15 8/30/2 B16 8/30/2 B17 8/30/2 B18 8/30/2 B19 8/30/2 B20 8/30/2 B21 8/30/2 B22 8/30/2 B23 8/30/2 B24 8/30/2 B25 status message : status message ADDRESSING direct direct direct/auto-increments to 03 direct/auto-increments to 04 direct/auto-increments to 05 direct/auto-increments to 06 direct/auto-increments to 07 direct/auto-increments to 08 direct/auto-increments to 09 direct/auto-increments to 0A direct/auto-increments to 0B direct/auto-increments to 0C direct/auto-increments to 0D direct/auto-increments to 0E direct/auto-increments to 0F stop value direct direct/auto-increments to 12 direct/auto-increments to 13 direct/auto-increments to 14 direct/auto-increments to 15 direct/auto-increments to 16 direct/auto-increments to 17 direct/auto-increments to 18 direct/auto-increments to 19 direct/auto-increments to 1A direct/auto-increments to 1B direct/auto-increments to 1C direct/auto-increments to 1D direct/auto-increments to 1E direct/auto-increments to 1F direct/auto-increments stop value
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
Register 00:Control/Status (reset state XXX0 XX00)
SAA5233
Register 00 is split into two parts. The control part (WRITE only) consisting of bits D4, D1 and D0 and status part (READ only) consisting of bits D7 to D5. Table 6 Register 00. D7 - DSQ D6 - 8/30/2 RF D5 - VPS RF D4 IEL - D3 - - D2 - - D1 ACQ 8/30/2 - D0 ACQ VPS -
Table 7 Register 00 bit description. SYMBOL IEL BIT D4 FUNCTION Interrupt Error Level. When logic 0, signal only completely valid data lines from Teletext packet 8/30/2 received and VPS received flags. When logic 1, signal valid framing code and Teletext packet header 8/30/2 received or valid start codeword for VPS received. Acquire 8/30/2. Acquire VPS. Allows selective decoding of either Teletext packet 8/30/2 data or VPS data. If both are set to the same value the system automatically selects the format being transmitted (see Table 8). Data Signal Quality. When logic 1, good Teletext or VPS data signal is being received. When logic 0, no Teletext or VPS data signal is being received. 8/30/2 Received Flag. When logic 1, and IEL (D4) = logic 0 an error-free Teletext packet 8/30/2 has been received, Hamming decoded and stored in the RAM. When logic 1, and IEL(D4) = logic 1 a Teletext packet with a valid framing code and 8/30/2 header has been received, Hamming decoded and stored in RAM. When logic 0 no Teletext packet 8/30/2 data received. VPS Received Flag. When logic 1, and IEL(D4) = logic 0, an error-free VPS data line has been received, biphase decoded and stored in the RAM. When logic 1, and IEL(D4) = logic 1 a VPS data line with valid start code has been received, biphase decoded and stored in RAM. When logic 0 no VPS data received.
ACQ 8/30/2 ACQ VPS
D1 D0
DSQ
D7
8/30/2 RF
D6
VPS RF
D5
Table 8 Selection of Teletext packet 8/30/2 data or VPS data. ACQ 8/30/2 0 0 1 1 ACQ VPS 0 1 0 1 FUNCTION use automatic selection algorithm for line 16 acquire only VPS data on every VBI line acquire only 8/30/2 data on every line 16 use automatic selection algorithm for line 16
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
Register 01: Interrupt (reset state X00X XXXX) Register R01 is WRITE only. Table 9 Register 01. D7 - D6 8/30/2 IE D5 VPS IE D4 - D3 - D2 - D1 -
SAA5233
D0 -
Table 10 Register 01 bit description. SYMBOL 8/30/2 IE BIT D6 FUNCTION 8/30/2 Interrupt Enable. This allows the reception of Teletext packet 8/30/2 data to be signalled on the INT pin. When logic 0 reception of Teletext packet 8/30/2 data is not signalled on INT pin. When logic 1 reception of Teletext packet 8/30/2 data is signalled on INT pin. VPS Interrupt Enable. This allows the reception of VPS data to be signalled on the INT pin. When logic 0 reception of VPS data is not signalled on INT pin. When logic 1 reception of VPS data is signalled on INT pin.
VPS IE
D5
Register 02 to 0F (HEX): VPS data bytes A single VPS data bytes is stored as two memory bytes, the least significant nibble of both memory bytes is the data making up the single VPS data byte. The most significant nibble of each memory byte is used to indicate a biphase error in the least significant nibble. This is indicated by the least significant bit being set, the top three bits are not used and are fixed to logic 0 (see Table 11). Table 11 VPS data bytes. ADDRESS (HEX) 02 03 Note 1. Equivalent to VPS B5 0101 1100 (MSB to LSB). Table 12 Register 02. D7 - D6 - D5 - D4 BIPHASE ERROR BIT D3 DATA BIT 3 D2 D1 D0 DATA BIT 0 REGISTER VPS B5 least significant nibble VPS B5 most significant nibble DATA 0000 1100(1) 0000 0101(1)
DATA BIT 2 DATA BIT 1
Register 11 to 1D (HEX): Teletext packet 8/30/2 data bytes Data is stored as single bytes. The four least significant bits represent the data. The fifth bit if set indicates a Hamming error in the stored data. The top three bits of the byte are not used and are fixed to logic 0. Table 13 Register 11. D7 - D6 - D5 - D4 HAMMING ERROR BIT 13 D3 DATA BIT 3 D2 D1 D0 DATA BIT 0
DATA BIT 2 DATA BIT 1
June 1994
Philips Semiconductors
Objective specification
Dual standard PDC decoder
Register 1E to 31D (HEX): Status display message
SAA5233
Data is stored as bytes which represent a Teletext character. The data is odd parity checked, if a parity error occurs this causes the byte not to be written to the RAM. The MSB is not used and is fixed to logic 0. Table 14 Register 11. D7 - D6 DATA BIT 6 D5 DATA BIT 5 D4 DATA BIT 4 D3 DATA BIT 3 D2 DATA BIT 2 D1 DATA BIT 1 D0 DATA BIT 0
I2C-bus slave address The slave address for the device can take one of two values dependent on the state of the input pin AD. Table 15 Device address. AD 0 1 Note 1. Where X is the R/W bit. I2C-bus increment The I2C-bus will also increment between registers as listed in Table 16 SLAVE ADDRESS 0010 001X(1) 0010 000X(1)
Table 16 Increment between registers. ADDRESS CONTENTS
02 to 0F (HEX) VPS data bytes 11 to 31 (HEX) Teletext packet 8/30/2 data bytes and Status display message Addressing any register in either of these ranges will initialize an increment until the final stop value provided each byte is acknowledged by the receiver. Initialization during power-up The device has an internal power-on reset unit which is used to reset the I2C-bus interface to be a slave transceiver. It also initializes the device to receive only completely valid Teletext packet 8/30/2 and VPS data. The interrupt signals for both Teletext packet 8/30/2 and VPS are disabled.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
APPLICATION INFORMATION
SAA5233
handbook, full pagewidth
video input 100 nF
100 nF
1
CVBS
VSS5
16
5V 4.7 k INT to microcontroller
2
BLACK
INT
15
220
27 k
3
IREF
AD
14
5V 100 nF 33 F
4
VDD
SDA
13
(1)
SAA5233
5 VSS1 SCL 12
I 2 C bus to microcontroller
6 15 pF 4.7 H 8 27 MHz 3rd overtone 10 pF 100 nF
OSCOUT
VSS4
11
7
OSCIN
VSS3
10
3.3 k
OSCGND
VSS2
MLB728
9
(1) I2C-bus address 0010 001R/W.
Fig.5 Application diagram; DIL16.
Table 17 Crystal characteristics. SYMBOL Crystal (27 MHz, 3rd overtone) C1 C0 CL Rr R1 Xa Xj Xd series capacitance parallel capacitance load capacitance resonance resistance series resistance ageing adjustment tolerance drift 1.7 5.2 20 - 20 - - - - - - 50 - 5 x 10-6 25 x 10-6 25 x 10-6 pF pF pF year-1 PARAMETER TYP. MAX. UNIT
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
PACKAGE OUTLINES
SAA5233
seating plane
handbook, full pagewidth
22.00 21.35 3.7 4.7 max max
8.25 7.80
3.9 3.4
0.51 min 2.2 max
2.54 (7x) 1.4 max
0.53 max
0.254 M
0.32 max 7.62 9.5 8.3
MSA254
16
9 6.48 6.14
1
8
Dimensions in mm.
Fig.6 Plastic dual in-line package; 16 leads (300 mil); DIP16, SOT38-1.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
handbook, full pagewidth
13.0 12.6
7.6 7.4
A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
20
11 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 1.1 0.5 detail A 2.65 2.35
pin 1 index 1 10 0 to 8
o
MBC234 - 1
1.27
0.49 0.36
0.25 M (20x)
Dimensions in mm.
Fig.7 Plastic small outline package; 20 leads; large body; SO20L, SOT163-1.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low-voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW
SAA5233
Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
June 1994
18
Philips Semiconductors
Objective specification
Dual standard PDC decoder
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5233
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
June 1994
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD32 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/01/1500/pp20 Document order number: Date of release: June 1994 9397 736 20011
Philips Semiconductors

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